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This paper presents the virtual environment implementation for project simulation and conception of supervision and control systems for mobile robots, that are capable to operate and adapting in different environments and conditions. This virtual system has as purpose to facilitate the development of embedded architecture systems, emphasizing the implementation of tools that allow the simulation of...
Supporting high levels of security in wireless networks is a challenging issue because of the specific problems this environment poses; the provided security by small mobile systems, such as PDAs and mobile phones, is often restricted by their limited battery power and their limited processing power. Driven by these restrictions, the designer will have to decide whether to implement the wireless network...
This work describes a hardware architecture implementation of an associative memory neural network (AMNN) using reconfigurable hardware devices such as FPGA (field programmable gates arrays) and its applications in image pattern recognition systems. An associative memory is a content-addressable structure that maps specific input representations to specific output representations. It is a system that...
Abstract This contribution proposes a secure and efficient method for updating reconfigurable hardware devices like FPGAs by using trusted computing technology. An interesting application is latent in the domain of embedded systems like in the automotive sector when durable products shall be updated in the field while stringent safety and security constraints have to be met. We propose an architecture...
Real-time scheduling for FPGAs presents unique challenges to traditional real-time scheduling theory, since it is similar to, but more general than multi-processor scheduling. In his paper, we address two problems of static task scheduling on a partially runtime reconfigurable FPGA: finding an optimal static schedule for a task graph with the optimization objective of minimizing the total schedule...
Reconfigurable devices, such as field programmable gate arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially runtime-reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling...
Custom hardware acceleration of electromagnetics computation leverages favorable industry trends, which indicate reconfigurable hardware devices such as field-programmable gate arrays (FPGAs) may soon outperform general-purpose CPUs. We present a new striping method for efficient sparse matrix-vector multiplication implemented in a deeply pipelined FPGA design. The effectiveness of the new method...
Custom hardware acceleration of electromagnetics computations leverages favorable industry trends, which indicate reconfigurable hardware devices such as field programmable gate arrays (FPGAs) may soon outperform general purpose CPUs. We present a new striping method for efficient sparse matrix-vector multiplication implemented in a deeply pipelined FPGA design. The effectiveness of the new method...
With the proliferation of computationally demanding embedded applications and the emergence of reconfigurable hardware devices, embedded systems would soon be designed around hybrid computational platforms consisting of a general-purpose processor and a reconfigurable logic unit. Such units can be reconfigured, often on the fly, to enhance the execution performance of various embedded applications...
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